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m0519 nov. 02 , 201 6 page 1 of 69 rev 1 .0 2 m0519 datasheet arm ? cortex ? - m 0 32 - bit microcontroller numicro ? family m0519 series datasheet the information described in this document is the exclusive intellectual property of nuvoton technology corporation and shall not be reproduced without permission from nuvoton. nuvoton is providing this document only for reference purposes of numicro microcontroller based system design. nuvoton assumes no responsibility for errors or omissions. all data and specifications are subject to change without notice. for additional information or questions, please contact: nuvoton technology corporation. www.nuvoton.com
m0519 nov. 02 , 201 6 page 2 of 69 rev 1 .0 2 m0519 datasheet table of c ontents 1 general description ................................ ................................ ....... 6 2 features ................................ ................................ ......................... 7 3 abbreviations ................................ ................................ ................ 10 4 parts information list and pin configuration .............................. 12 numicro ? m0519 selection guide ................................ ................................ .. 12 4.1 pin configuration ................................ ................................ ...................... 13 4.2 pi n description ................................ ................................ ........................ 16 4.3 5 block diagram ................................ ................................ ............... 23 6 functional description ................................ ................................ . 24 arm ? cortex ? - m0 core ................................ ................................ .............. 24 6.1 system manager ................................ ................................ ...................... 26 6.2 clock controller ................................ ................................ ....................... 35 6.3 flash memory controller (fmc) ................................ ................................ .... 38 6.4 general purpose i/o (gpio) ................................ ................................ ........ 39 6.5 timer controller (timer) ................................ ................................ ............ 40 6.6 basic pwm generator and capture timer (bpwm) ................................ ............ 41 6.7 enhanced pwm generator (epwm) ................................ .............................. 42 6.8 enhanced input capture timer (ecap) ................................ ........................... 43 6.9 watchdog timer (wdt) ................................ ................................ .............. 44 6.10 window watchdog timer (wwdt) ................................ ................................ 45 6.11 universal asynchronous receiver transmitter (uart) ................................ ........ 46 6.12 i 2 c serial interface controller (i2c) ................................ ................................ 47 6.13 serial peripheral interface (spi) ................................ ................................ .... 48 6.14 hardware divider (hdiv) ................................ ................................ ............ 49 6.15 enhanced analog - to - digital converter (eadc) ................................ .................. 50 6.16 analog comparator (acmp) ................................ ................................ ........ 51 6.17 op amplifier (opa) ................................ ................................ ................... 52 6.18 7 electrical characteristics ................................ .......................... 53 absolute maximum ratings ................................ ................................ ......... 53 7.1 dc electrical characteristics ................................ ................................ ........ 54 7.2 ac electrical characteristics ................................ ................................ ........ 58 7.3 analog characteristics ................................ ................................ ............... 60 7.4
m0519 nov. 02 , 201 6 page 3 of 69 rev 1 .0 2 m0519 datasheet flash dc electrical characteristics ................................ ................................ 64 7.5 8 package dimensions ................................ ................................ ...... 65 lqfp 100v (14x14x1.4 mm footprint 2.0mm) ................................ ................... 65 8.1 lqfp 64s (7x7x1.4 mm footprint 2.0 mm) ................................ ....................... 66 8.2 lqfp 48l (7x7x1.4mm footprint 2.0mm) ................................ ......................... 67 8.3 9 revision history ................................ ................................ ............ 68
m0519 nov. 02 , 201 6 page 4 of 69 rev 1 .0 2 m0519 datasheet list of figures figure 4 - 1 numicro ? m0519 selection code ................................ ................................ ........ 12 figure 4 - 2 numicro ? m0519vxxae series lqfp - 100 pin diagram ................................ ..... 13 figure 4 - 3 numicro ? m0519sxxae series lqfp - 64 pin diagram ................................ ....... 14 figure 4 - 4 numicro ? m0519lxxae series lqfp - 48 pin diagram ................................ ........ 15 figure 5 - 1 numicro ? m0519 series block diagram ................................ .............................. 23 figure 6 - 1 functional controller diagram ................................ ................................ ............ 24 figure 6 - 2 numicro ? m0519 series power distribution diagram ................................ .......... 27 figure 6 - 3 clock generator block diagram ................................ ................................ ......... 36 figure 6 - 4 clock generator global view diagram ................................ ............................... 37 figure 7 C 1 typical crystal application circuit ................................ ................................ ...... 58
m0519 nov. 02 , 201 6 page 5 of 69 rev 1 .0 2 m0519 datasheet list of tables table 6 - 1 address space assignments for on - chip controllers ................................ .......... 29 table 6 - 2 exception model ................................ ................................ ................................ .. 32 ta ble 6 - 3 system interrupt map vector table ................................ ................................ ...... 33 table 6 - 4 vector table ................................ ................................ ................................ ........ 34 table 6 - 5 clock stable count value table ................................ ................................ .......... 35
m0519 nov. 02 , 201 6 page 6 of 69 rev 1 .0 2 m0519 datasheet 1 general description the numicro ? m0519 series 32 - bit microcontroller is embedded with the newest arm ? cortex ? - m0 core at a cost equivalent to traditional 8 - bit microcontroller for industrial control and applications which need high performance. the numicro ? m0519 series embed ded with the cortex ? - m0 core run s up to 72 mhz and support s a variety of industrial control and applications which need high cpu performance. t he numicro ? m0519 series provides 128k/ 64 k byte s embedded flash, 4 kbyte s data flash, 8 kbyte s flash for the isp, and 16 k byte s embedded sram. this mcu includes advanced pwm function and input capture timer which are specially designed for motor driving application . it is also equip ped with plenty of peripheral devices, such as timers, watchdog tim er, uart, spi, i2c, pwm timer, gpio, 12 - bit adc, low voltage detector and brown - out detector. these useful functions make the numicro ? m0519 series powerful for a wide range of applications. in addition, t he numicro ? m0519 series is equipped with isp (in - system p rogramming) , icp (in - circuit programming) functions and iap (in - application programming) which allow user to update the program memory without removing the chip from the actual end product.
m0519 nov. 02 , 201 6 page 7 of 69 rev 1 .0 2 m0519 datasheet 2 features ? core C arm ? cortex ? - m0 core run ning up to 72 mhz C one 24 - bit system timer C supports l ow p ower s leep mode by wfi instructions C single - cycle 32 - bit hardware multiplier C supports programmable 4 level priorities of nested vectored interrupt controller ( nvi c) C supports serial wire debug (swd) suppor t with two watchpoints and four breakpoints ? buil t - in ldo for wide operating voltage range d from 2.5v to 5.5v ? m emory C 128k/64k bytes flash for program memory (aprom) C 4 kb flash for data memory (data flash) C 8 kb flash for loader (ldrom) C supports in - system program (isp) and in - application program (iap) application code update C supports 2 - wire d icp update through swd/ice interface C supports fast parallel programming mode by external programmer C 16k bytes embedded sram ? clock control C built - in 22.1184 mhz i nternal h igh s peed rc o scillator (hirc) f or system operation (variation < 2% at - 40 ?c ~ +105?c ) C built - in 10 khz internal low speed rc oscillator (lirc) for watchdog timer and w ake - up operation C built - in 4~24 mhz external high speed crystal oscillator (hxt) for precise timing operation C supports one pll up to 72 mhz for high performance system operation , sourced from hirc and hxt C supports clock out put ? hardware divider C supports signed 32 - bit dividend, 16 - bit divisor operation ? gpio port C four i/o modes: C ttl/schmitt trigger input selectable C bit control available C i/o pin configured as interrupt source with edge/level trigger setting C supports h igh driver and high sink current i / o (up to 16 ma at 5v) C int0 and int1 pins with individual interrupt vectors C supports u p to 82/51/38 gpios for lqfp 100 / 64 / 48 respectively ? timers C supports 4 sets of 32 - bit timers with 24 - bit up - timer and one 8 - bit prescale counter C provides o ne - shot, p eriodic, t oggle and c ontinuous c ounting operation modes C supports event counting function to count the event from external pin ? watchdog timer C supports m ultiple clock sources from lirc (default selection) and hclk/2048 C 8 selectable time - out period from 1. 6ms ~ 26 .0sec (depend ing on clock source) C able to wake up from power - down or i dle mode C interrupt or reset selectable on watchdog time - out C time - out reset delay period time can be selected ? window watchdog ti mer
m0519 nov. 02 , 201 6 page 8 of 69 rev 1 .0 2 m0519 datasheet C supports m ultiple clock sources from hclk/2048 (default selection) and lirc C w indow set by 6 - bit counter with 11 - bit prescale C able to wake up from p ower - down or i dle mode ? basic pwm C 1 unit of 16 - bit basic pwm, up to 2ch output C alternative function as input capture timer ? enhanced pwm C 2 units of 16 - bit enhanced pwm, up to 6ch output with dead - zone control, brake and polarity control for motor drive C default tri - state during any reset ? enhanced input capture C up to 2 units of 24 - bit input capture C each unit has 3 inputs: ecapx_ ic0, ecapx_ ic1 and ecapx_ ic2 ? uart C up to two 16550 compatible uart devices C programmable baud - rate generator C buffered receiving and transmitting, each with 16 bytes fifo C supports flow control (tx, rx, cts and rts) C supports irda(sir) function C supports rs - 485 ? spi C up to three sets of spi device C supports spi master/slave mode C full duplex synchronous serial data transfer C variable length of transfer data from 8 to 32 bits C msb or lsb first data transfer C rx and tx on both rising or falling edge of serial clock independently C support s byte suspend mode in 32 - bit transmission ? i 2 c C master/ slave up to 1 mbit/s C bi - directional data transfer between masters and slaves C multi - master bus (no central master) C arbitration between simultaneously transmitting masters C programmable clocks allow versatile rate control C multiple address recognition (four slave address with mask option) ? adc C two a/d converters C each adc with up to 8 channel, 12 - bit resolution with 10 - bit accuracy C 16 result registers C sampling rate up to 800ksps C two operati ng modes: ? single sampling mode: only one specified channel can be sampled at one time. ? simultaneous sampling mode: allowing two adc channels to be sampled simultaneously. C two converting result digital comparators C conversion start by software, external pins, or linked with timer 0~3 or pwm module ? up to three analog comparators ? up to two opa (operati onal amplifier )
m0519 nov. 02 , 201 6 page 9 of 69 rev 1 .0 2 m0519 datasheet ? brown - out detector C 4 levels: 4.4v/3.7v/2.7v/2.2v C optional brown - out interrupt or reset ? built - in ldo for wide operating voltage range: 2.5v to 5.5v ? low voltage reset ? 96 - bit unique id ? operating temperature: - 40 ~105 ? develop tools: parallel writer or in - circuit programming (icp) writer ? packages: C all green package (rohs) C lqfp 100/64/48 - pin
m0519 nov. 02 , 201 6 page 10 of 69 rev 1 .0 2 m0519 datasheet 3 abbreviations acronym description acmp analog comparator controller adc analog - to - digital converter aes advanced encryption standard apb advanced peripheral bus ahb a dvanced h igh - p erformance b us bod brown - out detection can controller area network dap debug access port des data encryption standard ebi external bus interface epwm enhanced pulse width modulation fifo first in, first out fmc flash memory controller fpu floating - point unit gpio general - purpose input/output hclk the clock of a dvanced h igh - p erformance b us hirc 22.1184 mhz i nternal h igh s peed rc o scillator hxt 4~24 mhz e xternal h igh s peed c rystal o scillator iap in application programming icp in circuit programming isp in system programming ldo low dropout regulator lin local interconnect network lirc 10 khz internal low speed rc oscillator (lirc) mpu memory protection unit nvic nested vectored interrupt controller pclk the clock of advanced peripheral bus pdma peripheral direct memory access pll phase - locked loop pwm pulse width modulation qei quadrature encoder interface sdio secure digital input/output spi serial peripheral interface
m0519 nov. 02 , 201 6 page 11 of 69 rev 1 .0 2 m0519 datasheet sps samples per second tdes triple data encryption standard tmr timer controller uart universal asynchronous receiver/transmitter ucid unique customer id usb universal serial bus wdt watchdog timer wwdt window watchdog timer
m0519 nov. 02 , 201 6 page 12 of 69 rev 1 .0 2 m0519 datasheet 4 parts information li st and pin configura tion numicro ? m0519 selection guide 4.1 4.1.1 numicro ? m0519 selection guide part n umber aprom ( kb ) ram ( kb ) data flash ( kb ) ld rom ( kb ) i/o timer (3 2 - b it ) connectivity capture pwm adc (1 2 - b it ) opa comp. isp / icp /iap package uart spi i 2 c lin m0519l d3 ae 64 16 4 8 38 4 2 1 1 2 - 6 x2, 16 - ch 2 2 v lqfp48 m0519l e3ae 128 16 config . 8 38 4 2 1 1 2 - 6 x2, 16 - ch 2 2 v lqfp48 m0519 s d 3 ae 64 16 4 8 51 4 2 2 1 2 - 10 x2, 16 - ch 2 2 v lqfp64 m0519 s e3ae 128 16 config . 8 51 4 2 2 1 2 - 10 x2, 16 - ch 2 2 v lqfp64 m0519ve3 ae 128 16 config . 8 82 4 2 3 1 2 6 14 x2, 16 - ch 2 3 v lqfp100 4.1.2 numicro ? m0519 naming rule figure 4 - 1 numicro ? m 0519 selection code c p u c o r e a r m c o r t e x m 0 p a c k a g e t y p e l : l q f p 4 8 ( 7 x 7 ) f l a s h r o m d : 6 4 k b f l a s h r o m e : 1 2 8 k b f l a s h r o m t e m p e r a t u r e e : - 4 0 ~ + 1 0 5 v e r s i o n a : v e r s i o n m 0 5 1 9 - x x e s : l q f p 6 4 ( 7 x 7 ) x x s r a m s i z e 3 : 1 6 k b s r a m v : l q f p 1 0 0 ( 1 4 x 1 4 )
m0519 nov. 02 , 201 6 page 13 of 69 rev 1 .0 2 m0519 datasheet p in c onfiguration 4.2 4.2.1 lqf p 100 - pin figure 4 - 2 numicro ? m0519 v xx ae series lqfp - 100 pin diagram a d c 1 _ c h 6 / p 7 . 6 a c m p 2 _ p / a d c 1 _ c h 5 / p 7 . 5 a c m p 2 _ n / a d c 1 _ c h 4 / p 7 . 4 p 3 . 6 i 2 c _ s c l / t m 1 / p 3 . 5 i 2 c _ s d a / t m 0 / p 3 . 4 e p w m 1 _ b r a k e 0 / p 1 . 7 i n t 0 / p 3 . 2 l d o _ c a p v d d v s s i 2 c _ s c l / u a r t 1 _ r x d / p a . 1 e p w m 1 _ c h 3 / p 1 . 3 e p w m 1 _ c h 2 / p 1 . 2 p 4 . 4 p 4 . 5 e c a p 1 _ i c 0 / p 4 . 0 e c a p 1 _ i c 1 / p 4 . 1 e c a p 1 _ i c 2 / p 4 . 2 o p 1 _ p / p 9 . 2 v d d v s s p 8 . 5 e p w m 1 _ b r a k e 1 / p 9 . 3 n r e s e t x t 1 _ o u t x t 1 _ i n s p i 1 _ m o s i / p 9 . 6 v r e f a v d d a v s s p 8 . 0 / o p 0 _ p p 8 . 1 / o p 0 _ n p 8 . 2 / o p 0 _ o p 6 . 2 / a d c 0 _ c h 2 p 6 . 3 / a d c 0 _ c h 3 p 6 . 4 / a d c 0 _ c h 4 / a c m p 1 _ n p 6 . 5 / a d c 0 _ c h 5 / a c m p 1 _ p p 6 . 6 / a d c 0 _ c h 6 p 6 . 7 / a d c 0 _ c h 7 v d d v s s a d c 1 _ c h 2 / p 7 . 2 i c e _ d a t i c e _ c l k s p i 1 _ m i s o / p 9 . 5 p 0 . 4 / e p w m 0 _ c h 4 p 0 . 5 / e p w m 0 _ c h 5 p 0 . 6 / e p w m 0 _ b r a k e 1 p 0 . 7 / s t a d c p 2 . 6 / s p i 0 _ s s / u a r t 1 _ n c t s p 2 . 7 / s p i 0 _ c l k / u a r t 1 _ n r t s p 5 . 1 / s p i 0 _ m i s o / u a r t 0 _ n c t s / i 2 c _ s d a p 5 . 0 / s p i 0 _ m o s i / u a r t 0 _ n r t s / i 2 c _ s c l v s s v d d p 4 . 7 / t m 3 p 3 . 1 / u a r t 0 _ t x d / a c m p 0 _ o p 3 . 0 / u a r t 0 _ r x d / c l k o p 1 . 0 / e p w m 1 _ c h 0 p 1 . 1 / e p w m 1 _ c h 1 p 4 . 6 / t m 2 2 6 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 1 0 0 9 9 9 8 9 7 9 6 9 5 9 4 9 3 9 2 9 1 9 0 8 9 8 8 8 7 8 6 8 5 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 6 0 6 1 6 2 6 3 6 4 6 5 6 6 6 7 6 8 6 9 7 0 7 1 7 2 7 3 7 4 7 5 p 8 . 6 p 8 . 7 / a c m p 0 _ o m 0 5 1 9 v x x a e l q f p 1 0 0 - p i n 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 p v s s s p i 1 _ s s / p 9 . 7 p 3 . 7 i 2 c _ s d a / u a r t 1 _ t x d / p a . 0 b p w m 0 _ c h 1 / p 5 . 7 b p w m 0 _ c h 0 / p 5 . 6 e p w m 0 _ b r a k e 0 / p 1 . 6 e p w m 1 _ c h 5 / p 1 . 5 e p w m 1 _ c h 4 / p 1 . 4 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0 p 3 . 3 / i n t 1 p 4 . 3 p 2 . 4 p 2 . 5 p 5 . 2 / s p i 2 _ m i s o / a c m p 1 _ o p 2 . 0 / s p i 2 _ m o s i / a c m p 2 _ o p 2 . 1 / e c a p 0 _ i c 2 p 2 . 2 / e c a p 0 _ i c 1 p 2 . 3 / e c a p 0 _ i c 0 5 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 p 6 . 0 / a d c 0 _ c h 0 p 6 . 1 / a d c 0 _ c h 1 p 0 . 0 / e p w m 0 _ c h 0 / e c a p 1 _ i c 0 p 0 . 1 / e p w m 0 _ c h 1 / e c a p 1 _ i c 1 p 0 . 2 / e p w m 0 _ c h 2 / e c a p 1 _ i c 2 p 0 . 3 / e p w m 0 _ c h 3 / s t a d c p 5 . 5 / c l k o p 5 . 4 / s p i 2 _ s s p 5 . 3 / s p i 2 _ c l k 8 4 8 3 8 2 8 1 8 0 7 9 7 8 7 7 7 6 s p i 1 _ c l k / p 9 . 4 a d c 1 _ c h 1 / p 7 . 1 a d c 1 _ c h 0 / p 7 . 0 a c m p 0 _ p / p 8 . 4 a c m p 0 _ n / p 8 . 3 o p 1 _ o / p 9 . 0 o p 1 _ n / p 9 . 1 a d c 1 _ c h 3 / p 7 . 3 a d c 1 _ c h 7 / p 7 . 7
m0519 nov. 02 , 201 6 page 14 of 69 rev 1 .0 2 m0519 datasheet 4.2.2 lqfp 64 - pin figure 4 - 3 numicro ? m0519 s x xae series lqfp - 64 pin diagram 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 6 4 6 3 6 2 6 1 6 0 5 9 5 8 5 7 5 6 5 5 5 4 5 3 5 2 5 1 5 0 4 9 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 m 0 5 1 9 s x x a e l q f p 6 4 - p i n a d c 1 _ c h 6 / p 7 . 6 a c m p 2 _ p / a d c 1 _ c h 5 / p 7 . 5 a c m p 2 _ n / a d c 1 _ c h 4 / p 7 . 4 i 2 c _ s c l / t 1 / p 3 . 5 i 2 c _ s d a / t 0 / p 3 . 4 e p w m 1 _ b r a k e 0 / p 1 . 7 i n t 0 / p 3 . 2 l d o _ c a p v d d v s s i 2 c _ s c l / u a r t 1 _ r x d / p a . 1 e p w m 1 _ c h 3 / p 1 . 3 e p w m 1 _ c h 2 / p 1 . 2 o p 1 _ p / p 9 . 2 n r e s e t x t 1 _ o u t x t 1 _ i n a v d d a v s s p 6 . 2 / a d c 0 _ c h 2 p 6 . 3 / a d c 0 _ c h 3 p 6 . 4 / a d c 0 _ c h 4 / a c m p 1 _ n p 6 . 5 / a d c 0 _ c h 5 / a c m p 1 _ p p 6 . 6 / a d c 0 _ c h 6 p 6 . 7 / a d c 0 _ c h 7 a d c 1 _ c h 2 / p 7 . 2 i c e _ d a t i c e _ c l k p 0 . 4 / e p w m 0 _ c h 4 p 0 . 5 / e p w m 0 _ c h 5 p 2 . 6 / s p i 0 _ s s / u a r t 1 _ n c t s p 2 . 7 / s p i 0 _ c l k / u a r t 1 _ n r t s p 5 . 1 / s p i 0 _ m i s o / u a r t 0 _ n c t s / i 2 c _ s d a p 5 . 0 / s p i 0 _ m o s i / u a r t 0 _ n r t s / i 2 c _ s c l v s s v d d p 3 . 1 / u a r t 0 _ t x d p 3 . 0 / u a r t 0 _ r x d / c l k o p 1 . 0 / e p w m 1 _ c h 0 p 1 . 1 / e p w m 1 _ c h 1 i 2 c _ s d a / u a r t 1 _ t x d / p a . 0 b p w m 0 _ c h 1 / p 5 . 7 b p w m 0 _ c h 0 / p 5 . 6 e p w m 0 _ b r a k e 0 / p 1 . 6 e p w m 1 _ c h 5 / p 1 . 5 e p w m 1 _ c h 4 / p 1 . 4 p 2 . 4 p 2 . 5 p 5 . 2 / s p i 2 _ m i s o / a c m p 1 _ o p 2 . 0 / s p i 2 _ m o s i / a c m p 2 _ o p 6 . 0 / a d c 0 _ c h 0 p 6 . 1 / a d c 0 _ c h 1 p 5 . 4 / s p i 2 _ s s p 5 . 3 / s p i 2 _ c l k a d c 1 _ c h 1 / p 7 . 1 a d c 1 _ c h 0 / p 7 . 0 o p 1 _ o / p 9 . 0 o p 1 _ n / p 9 . 1 a d c 1 _ c h 3 / p 7 . 3 a d c 1 _ c h 7 / p 7 . 7 p 8 . 0 / o p 0 _ p p 8 . 1 / o p 0 _ n p 8 . 2 / o p 0 _ o v r e f
m0519 nov. 02 , 201 6 page 15 of 69 rev 1 .0 2 m0519 datasheet 4.2.3 lqfp 48 - pin figure 4 - 4 numicro ? m0519 l xx ae series lqfp - 48 pin diagram 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 4 8 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 3 9 3 8 3 7 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 3 6 m 0 5 1 9 l x x a e l q f p 4 8 - p i n a v d d a v s s p 8 . 0 / o p 0 _ p p 8 . 1 / o p 0 _ n p 8 . 2 / o p 0 _ o p 6 . 2 / a d c 0 _ c h 2 p 6 . 3 / a d c 0 _ c h 3 p 6 . 4 / a d c 0 _ c h 4 / a c m p 1 _ n p 6 . 5 / a d c 0 _ c h 5 / a c m p 1 _ p p 6 . 6 / a d c 0 _ c h 6 p 6 . 7 / a d c 0 _ c h 7 p 6 . 0 / a d c 0 _ c h 0 p 6 . 1 / a d c 0 _ c h 1 p 0 . 7 / s t a d c p 2 . 6 / s p i 0 _ s s / u a r t 1 _ n c t s p 2 . 7 / s p i 0 _ c l k / u a r t 1 _ n r t s p 5 . 1 / s p i 0 _ m i s o / u a r t 0 _ n c t s / i 2 c _ s d a p 5 . 0 / s p i 0 _ m o s i / u a r t 0 _ n r t s / i 2 c _ s c l p 3 . 1 / u a r t 0 _ t x d / a c m p 0 _ o p 3 . 0 / u a r t 0 _ r x d / c l k o a d c 1 _ c h 6 / p 7 . 6 a c m p 2 _ p / a d c 1 _ c h 5 / p 7 . 5 a c m p 2 _ n / a d c 1 _ c h 4 / p 7 . 4 o p 1 _ p / p 9 . 2 n r e s e t a d c 1 _ c h 2 / p 7 . 2 a d c 1 _ c h 1 / p 7 . 1 a d c 1 _ c h 0 / p 7 . 0 o p 1 _ o / p 9 . 0 o p 1 _ n / p 9 . 1 a d c 1 _ c h 3 / p 7 . 3 a d c 1 _ c h 7 / p 7 . 7 e p w m 1 _ b r a k e 0 / p 1 . 7 l d o _ c a p v d d v s s i 2 c _ s c l / u a r t 1 _ r x d / p a . 1 p 1 . 3 / e p w m 1 _ c h 3 p 1 . 2 / e p w m 1 _ c h 2 i 2 c _ s d a / u a r t 1 _ t x d / p a . 0 b p w m 0 _ c h 1 / p 5 . 7 b p w m 0 _ c h 0 / p 5 . 6 p 1 . 5 / e p w m 1 _ c h 5 p 1 . 4 / e p w m 1 _ c h 4 x t 1 _ o u t x t 1 _ i n i c e _ d a t i c e _ c l k
m0519 nov. 02 , 201 6 page 16 of 69 rev 1 .0 2 m0519 datasheet pin description 4.3 pin number pin name pin type [1] description 100 - pin 64 - p in 48 - p in 10 6 7 v dd p power supply: supply voltage digital v dd for operation. 34 61 21 89 11 7 8 v ss p ground: digital ground potential. 35 60 22 90 9 5 6 ldo_cap p ldo: ldo output pin note: it needs to be connected with a 1 uf capacitor. 1 - - pv ss p pll ground: pll ground potential. 7 4 47 36 av dd ap p ower supply for internal analog circuit 7 3 46 35 av ss ap ground pin for analog circuit 7 5 48 - v ref ap v oltage reference input for adc note: it needs to be connected with a 1uf capacitor. 9 3 60 48 n reset i (st) reset: nreset pin is a schmitt trigger input pin for hardware device reset. a low on this pin for 768 clock counter of internal rc 22.1184 mhz while the system clock is running will reset the device. nreset pin has an internal pull - up resistor allowing power - on reset by simply connecting an external capacitor to gnd . 9 4 61 4 xt 1 _out o crystal out : this is the output pin from the internal inverting amplifier. it emits the inverted signal of xt 1_in . 9 5 62 3 xt 1 _in i (st) crystal in : this is the input pin to the internal inverting amplifier. the system clock is from external crystal or resonator when fosc[1:0] (config3[1:0]) are both logic 1 by default. 96 63 2 ice_dat i/o serial wired debugger data pin 9 7 64 1 ice _ clk i serial wired debugger clock pin 57 - - p0.0 i/o general purpose digital i/o pin pwm0 _ch 0 o pwm0 output of pwm unit 0 ecap1_ ic 0 i input 0 of enhanced input capture unit 1 56 - - p0.1 i/o general purpose digital i/o pin pwm0 _ch 1 o pwm1 output of pwm unit 0 ecap1_ ic1 i input 1 of enhanced input capture unit 1 55 - - p0.2 i/o general purpose digital i/o pin pwm0 _ch 2 o pwm2 output of pwm unit 0
m0519 nov. 02 , 201 6 page 17 of 69 rev 1 .0 2 m0519 datasheet pin number pin name pin type [1] description 100 - pin 64 - p in 48 - p in ecap1_ ic2 i input 2 of enhanced input capture unit 1 54 - - p0.3 i/o general purpose digital i/o pin pwm0 _ch 3 o pwm3 output of pwm unit 0 stadc i adc external trigger input 45 30 - p0.4 i/o general purpose digital i/o pin pwm0 _ch 4 o pwm4 output of pwm unit 0 4 4 29 - p0.5 i/o general purpose digital i/o pin pwm0 _ch 5 o pwm5 output of pwm unit 0 43 - - p 0 . 6 i/o general purpose digital i/o pin pwm0_ b ra k e 1 i brake input pin 1 of pwm unit 0 42 - 23 p0.7 i/o general purpose digital i/o pin stadc i adc external trigger input 30 18 - p1.0 i/o general purpose digital i/o pin pwm1 _ch 0 o pwm0 output of pwm unit 1 29 17 - p1.1 i/o general purpose digital i/o pin pwm1 _ch 1 o pwm1 output of pwm unit 1 20 16 13 p1.2 i/o general purpose digital i/o pin pwm1 _ch 2 o pwm2 output of pwm unit 1 19 15 14 p1.3 i/o general purpose digital i/o pin pwm1 _ch 3 o pwm3 output of pwm unit 1 18 14 15 p1.4 i/o general purpose digital i/o pin pwm1 _ch 4 o pwm4 output of pwm unit 1 17 13 16 p1.5 i/o general purpose digital i/o pin pwm1 _ch 5 o pwm5 output of pwm unit 1 16 12 - p1. 6 i/o general purpose digital i/o pin pwm0_ b ra k e 0 i brake input pin 0 of pwm unit 0 8 4 5 p1.7 i/o general purpose digital i/o pin pwm1_ b ra k e 0 i brake input pin 0 of pwm unit 1 49 31 - p 2.0 i/o general purpose digital i/o pin spi2_ mosi i/o spi 2 mosi (master out, slave in) pin acmp2_ o ao analog c omparator 2 output pin 48 - - p2.1 i/o general purpose digital i/o pin ecap0_ ic2 i input 2 of enhanced input capture unit 0
m0519 nov. 02 , 201 6 page 18 of 69 rev 1 .0 2 m0519 datasheet pin number pin name pin type [1] description 100 - pin 64 - p in 48 - p in 47 - - p2.2 i/o general purpose digital i/o pin ecap0_ ic1 i input 1 of enhanced input capture unit 0 46 - - p2.3 i/o general purpose digital i/o pin ecap0_ ic0 i input 0 of enhanced input capture unit 0 41 28 - p2.4 i/o general purpose digital i/o pin 40 27 - p2.5 i/o general purpose digital i/o pin 3 9 26 22 p2.6 i/o general purpose digital i/o pin spi0_ ss i /o spi 0 slave select pin uart1_n cts i uart1 cts pin 3 8 25 21 p 2.7 i/o general purpose digital i/o pin spi 0 _clk i/o spi 0 serial clock pin uart1_n rts o uart1 rts pin 31 19 17 p 3.0 i/o general purpose digital i/o pin uart0_ rx d i data receiver input pin for uart0 32 20 18 p3.1 i/o general purpose digital i/o pin uart0_ tx d o data transmitter output pin for uart0 a c m p 0_ o ao analog comparator 0 output 7 3 - p3.2 i/o general purpose digital i/o pin int0 i external interrupt 0 input pin 27 - - p3.3 i/o general purpose digital i/o pin int1 i external interrupt 1 input pin 6 2 - p 3.4 i/o general purpose digital i/o pin t m 0 i /o timer 0 external clock i2c 0 _ sda i/ o i2c 0 data input/output pin 5 1 - p 3.5 i/o general purpose digital i/o pin t m 1 i /o timer 1 external clock i2c 0 _ scl i /o i2c 0 clock output pin 4 - - p3.6 i/o general purpose digital i/o pin 3 - - p3.7 i/o general purpose digital i/o pin 2 3 - - p4.0 i/o general purpose digital i/o pin ecap1_ ic0 i input 0 of enhanced input capture unit 1 2 4 - - p4.1 i/o general purpose digital i/o pin ecap1_ ic1 i input 1 of enhanced input capture unit 1
m0519 nov. 02 , 201 6 page 19 of 69 rev 1 .0 2 m0519 datasheet pin number pin name pin type [1] description 100 - pin 64 - p in 48 - p in 25 - - p4.2 i/o general purpose digital i/o pin ecap1_ ic 2 i input 2 of enhanced input capture unit 1 26 - - p4. 3 i/o general purpose digital i/o pin 21 - - p4.4 i/o general purpose digital i/o pin 22 - - p4.5 i/o general purpose digital i/o pin 28 - - p4.6 i/o general purpose digital i/o pin t m 2 i /o timer 2 external clock 33 - - p 4.7 i/o general purpose digital i/o pin t m 3 i /o timer 3 external clock 3 6 23 19 p 5.0 i/o general purpose digital i/o pin spi0_ mosi i/o spi 0 mosi (master out, slave in) pin uart0_n rts o uart0 rts pin 3 7 24 20 p 5.1 i/o general purpose digital i/o pin spi0_ miso i/o spi 0 miso (master in, slave out) pin uart0_n cts i uart0 cts pin 50 32 - p 5.2 i/o general purpose digital i/o pin spi2_ miso i/o spi 2 miso (master in, slave out) pin acm p 1_ o ao analog comparator 1 output pin 51 33 - p 5.3 i/o general purpose digital i/o pin spi 2 _clk i/o spi 2 serial clock pin 52 34 - p 5.4 i/o general purpose digital i/o pin spi2_ ss i/o spi 2 slave select pin 53 - - p5.5 i/o general purpose digital i/o pin clko o frequency divider output pin 15 11 12 p5.6 i/o general purpose digital i/o pin pwm2 _ch 0 i/ o pwm0 output of pwm unit 2 14 10 11 p5.7 i/o general purpose digital i/o pin pwm2 _ch 1 i/ o pwm1 output of pwm unit 2 6 9 42 31 p6.0 i/o general purpose digital i/o pin adc0_ch 0 ai adc analog input 0 for sample - and - hold a 6 8 41 30 p6.1 i/o general purpose digital i/o pin adc0_ch 1 ai adc analog input 1 for sample - and - hold a 6 7 40 29 p6.2 i/o general purpose digital i/o pin
m0519 nov. 02 , 201 6 page 20 of 69 rev 1 .0 2 m0519 datasheet pin number pin name pin type [1] description 100 - pin 64 - p in 48 - p in adc0_ch 2 ai adc analog input 2 for sample - and - hold a 6 6 39 28 p6.3 i/o general purpose digital i/o pin adc0_ch 3 ai adc analog input 3 for sample - and - hold a 6 5 38 27 p6.4 i/o general purpose digital i/o pin adc0_ch 4 ai adc analog input 4 for sample - and - hold a acmp1_ n ai analog comparator 1 negative input 6 4 37 26 p6.5 i/o general purpose digital i/o pin adc0_ch 5 ai adc analog input 5 for sample - and - hold a acmp1_ p ai analog comparator 1 positive input 6 3 36 25 p6.6 i/o general purpose digital i/o pin adc0_ch 6 ai adc analog input 6 for sample - and - hold a 6 2 35 24 p6.7 i/o general purpose digital i/o pin adc0_ch 7 ai adc analog input 7 for sample - and - hold a 8 3 56 44 p7.0 i/o general purpose digital i/o pin adc 1_ch 0 ai adc analog input 0 for sample - and - hold b 8 2 55 43 p7.1 i/o general purpose digital i/o pin adc 1_ch 1 ai adc analog input 1 for sample - and - hold b 8 1 54 42 p7.2 i/o general purpose digital i/o pin adc 1_ch 2 ai adc analog input 2 for sample - and - hold b 8 0 53 41 p7.3 i/o general purpose digital i/o pin adc 1_ch 3 ai adc analog input 3 for sample - and - hold b 79 52 40 p7.4 i/o general purpose digital i/o pin adc 1_ch 4 ai adc analog input 4 for sample - and - hold b acmp2_ n ai analog comparator 2 negative input 78 51 39 p7.5 i/o general purpose digital i/o pin adc 1_ch 5 ai adc analog input 5 for sample - and - hold b acmp2_ p ai analog comparator 2 positive input 77 50 38 p7.6 i/o general purpose digital i/o pin adc1_ch 6 ai adc analog input 6 for sample - and - hold b 76 49 37 p7.7 i/o general purpose digital i/o pin adc1_ch 7 ai adc analog input 7 for sample - and - hold b 7 2 45 34 p8.0 i/o general purpose digital i/o pin op 0_ p ai op amplifier 0 p ositive input
m0519 nov. 02 , 201 6 page 21 of 69 rev 1 .0 2 m0519 datasheet pin number pin name pin type [1] description 100 - pin 64 - p in 48 - p in 71 44 33 p8.1 i/o general purpose digital i/o pin op 0_ n ai op amplifier 0 n egative input 70 43 32 p8.2 i/o general purpose digital i/o pin op 0_ o ao op amplifier 0 output 85 - - p8.3 i/o general purpose digital i/o pin acmp0_ n ai analog comparator negative input pin 84 - - p8.4 i/o general purpose digital i/o pin acmp0_ p ai analog comparator p ositive input pin 91 - - p8.5 i/o general purpose digital i/o pin 59 - - p8.6 i/o general purpose digital i/o pin 58 - - p8.7 i/o general purpose digital i/o pin acmp0_ o o analog c omparator output pin 8 6 57 45 p9.0 i/o general purpose digital i/o pin op1_ o ao op amplifier 1 output 8 7 58 46 p9.1 i/o general purpose digital i/o pin op 1_ n ai op amplifier 1 n egative input 8 8 59 47 p9.2 i/o general purpose digital i/o pin op 1_ p ai op amplifier 1 p ositive input 9 2 - - p 9.3 i/o general purpose digital i/o pin pwm1_ b ra k e 1 i brake input pin 1 of pwm unit 1 98 - - p 9.4 i/o general purpose digital i/o pin spi 1 _clk i/o spi 1 serial clock pin 99 - - p 9.5 i/o general purpose digital i/o pin spi1_ miso i/o spi 1 miso (master in, slave out) pin 100 - - p 9.6 i/o general purpose digital i/o pin spi1_ mosi i/o spi 1 mosi (master out, slave in) pin 2 - - p9.7 i/o general purpose digital i/o pin spi1_ ss i/o spi1 slave select pin 13 9 10 pa.0 i/o general purpose digital i/o pin uart1_ tx d o data transmitter output pin for uart1 i2c 0 _ sda i/ o i2c 0 data input/output pin 12 8 9 pa.1 i/o general purpose digital i/o pin uart1_ rx d i data receiver input pin for uart1
m0519 nov. 02 , 201 6 page 22 of 69 rev 1 .0 2 m0519 datasheet pin number pin name pin type [1] description 100 - pin 64 - p in 48 - p in i2c 0 _ scl i /o i2c 0 clock output pin note: pin type i = digital input, o = digital output; ai = analog input; p = power pin; ap = analog power
m0519 nov. 02 , 201 6 page 23 of 69 rev 1 .0 2 m0519 datasheet 5 block diagram figure 5 - 1 numicro ? m0519 series block diagram bridge clock control hs osc. 22.1184 mhz ls osc. 10 khz hs ext. crystal osc. 4~24 mhz pll gpio general purpose i/o external interrupt reset pin power - on reset ldo power control brown - out detection lvr connectivity uart x 2 i2c spi x 3 2 sets of 12 - bit adc x 8 analog interface operating amp. x 2 comparators x 3 aprom 128/64 kb ldrom 8 kb data flash 4 kb sram 16 kb memory arm ? cortex ? - m0 72 mhz epwm timer x 12 watchdog timers bpwm timer x 2 timer / pwm 32 - bit timer x 4 icap timer x 2 ahb bus apb bus
m0519 nov. 02 , 201 6 page 24 of 69 rev 1 .0 2 m0519 datasheet 6 functional descripti on arm ? cortex ? - m0 c ore 6.1 the cortex ? - m0 processor is a configurable, multistage, 32 - bit risc processor , which has an amba ahb - lite interface and includes an nvic component. it also has optional hardware debug functionality. the processor can execute thumb code and is compatible with other cortex ? - m profile processor. the profile supports two modes - thread mode and handler mode. handler mode is entered as a result of an exception. an exception ret urn can only be issued in handler mode. thread mode is entered on reset, and can be entered as a result of an exception return. figure 6 - 1 shows the f unctional controller of processor. figure 6 - 1 functional controller diagram t he implemented device provides the following components and features: ? a low gate count processor: - armv6 - m thumb ? instruction set - thumb - 2 technology - armv6 - m compliant 24 - bit systick timer - a 32 - bit hardware multiplier - s ystem interface support ed with little - endian data accesses - a bility to have deterministic, fixed - latency, interrupt handling - load/store - mu ltiples and multicycle - multiplies that can be abandoned and restarted to facilitate rapid interrupt handling - c application binary interface compliant exception model. this is the armv6 - m, c application binary interface (c - abi) compliant exception model tha t enables the use of pure c functions as interrupt handlers - low p ower s leep mode entry using wait for interrupt (wfi), wait for event (wfe) instructions, or the return from interrupt sleep - on - exit feature ? nvic: c o r t e x t m - m 0 p r o c e s s o r c o r e n e s t e d v e c t o r e d i n t e r r u p t c o n t r o l l e r ( n v i c ) b r e a k p o i n t a n d w a t c h p o i n t u n i t d e b u g g e r i n t e r f a c e b u s m a t r i x d e b u g a c c e s s p o r t ( d a p ) d e b u g c o r t e x t m - m 0 p r o c e s s o r c o r t e x t m - m 0 c o m p o n e n t s w a k e u p i n t e r r u p t c o n t r o l l e r ( w i c ) i n t e r r u p t s s e r i a l w i r e o r j t a g d e b u g p o r t a h b - l i t e i n t e r f a c e
m0519 nov. 02 , 201 6 page 25 of 69 rev 1 .0 2 m0519 datasheet - 32 external interrupt inputs, each with four levels of priority - dedicated non - m askable interrupt (nmi) input - support s for both level - sensitive and pulse - sensitive interrupt lines - supports wake - up interrupt controller (wic) and , providing u ltra - low p ower s leep mode ? debug support - four hardware breakpoints - two watchpoints - program counter sampling register (pcsr) for non - intrusive code profiling - single step and vector catch capabilities ? bus interfaces: - single 32 - bit amba - 3 ahb - lite system interface that provides simple integration to all system pe ripherals and memory - single 32 - bit slave port that supports the dap (debug access port)
m0519 nov. 02 , 201 6 page 26 of 69 rev 1 .0 2 m0519 datasheet s ystem m anager 6.2 6.2.1 overview system management includes the following sections: ? system reset s ? system power distribution ? system memory map ? system management registers for part number id, chip reset and on - chip controllers reset , multi - functional pin control ? system timer (systick) ? nested vectored interrupt controller (nvic) ? system control register s 6.2.2 system reset the system reset can be issued by one of the following listed events. for these reset event flags can be read by rst s rc register. ? hardware reset ? power - o n reset (por) ? l ow level on the reset pin (nr e s e t) ? watchdog time - o ut reset (wdt) ? low voltage reset (lvr) ? brown - o ut detector reset (bod) ? software reset ? sys rese t - sysresetreq (aircr[2]) ? cortex ? - m0 core one - shot reset - cpu_rst (iprstc1[1]) ? c hip one - shot reset - chip_rst (iprstc1[0]) power - on reset or chip_rst (iprst1[0]) reset the whole chip including all peripherals, ext ernal crystal circuit and bs (ispcon[1]) bit. sysresetreq (aircr[2]) reset the whole chip including all peripherals, but does not reset external crystal circuit and bs (ispcon[1]) bit.
m0519 nov. 02 , 201 6 page 27 of 69 rev 1 .0 2 m0519 datasheet 6.2.3 system power distribution in this chip, the power distribution is divided into two segments. ? analog power from av dd and av ss provides the power for analog components operation. ? digital power from v dd and v ss supplies the power to the i/o pins and internal regulator which provides a fixed 1.8 v power for digital operation . the output of internal vol tage regulators, ldo_cap, requires an external capacitor which should be located close to the corresponding pin. analog power (av dd ) should be the same voltage level of the digital power (v dd ) . figure 6 - 2 numicro ? m0519 series power distribution diagram 1 2 - b i t s a r - a d c b r o w n - o u t d e t e c t o r l o w v o l t a g e r e s e t a n a l o g c o m p a r a t o r t e m p e r a t u r e s e n e o r f l a s h d i g i t a l l o g i c i n t e r n a l 2 2 . 1 1 8 4 m h z & 1 0 k h z o s c i l l a t o r a v d d a v s s l d o _ c a p 1 u f g p i o l d o p l l p o r 5 0 p o r 1 8 v d d v s s i o c e l l p v d d 1 . 8 v o p a 4 ~ 2 4 m h z c r y s t a l x t 1 _ i n x t 1 _ o u t
m0519 nov. 02 , 201 6 page 28 of 69 rev 1 .0 2 m0519 datasheet 6.2.4 system memory map the numicro ? m0519 series provides 4g - byte address ing space. the memory locations assigned to each on - chip controllers are shown in table 6 - 1 . the detailed register definition, memory space, and programming detailed will be described in the following sections for each on - chip periph eral. the numicro ? m0519 series only supports little - endian data format. address space token controllers flash and sram memory space 0x0000_0000 C 0x0001_ffff flash_ba flash memory space (128 kb) 0x2000_0000 C 0x2000_3fff sram_ba sram memory space (16 kb) ahb controllers space (0x5000_0000 C 0x501f_ffff) 0x5000_0000 C 0x5000_01ff gcr_ba system global control registers 0x5000_0200 C 0x5000_02ff clk_ba clock control registers 0x5000_0300 C 0x5000_03ff int_ba interrupt multiplexer control registers 0x5000_4000 C 0x5000_7fff gpio_ba gpio control registers 0x5000_c000 C 0x5000_ffff fmc_ba flash memory control registers 0x5001_4000 C 0x5001_7fff h div_ba hardware divider register apb1 controllers space (0x4000_0000 ~ 0x400f_ffff) 0x4000_4000 C 0x4000_7fff wdt_ba watchdog timer control registers 0x4000_4 1 00 C 0x4000_7fff w wdt_ba window watchdog timer control registers 0x4001_0000 C 0x4001_3fff tmr0 1 _ba timer0 /timer1 control registers 0x4002_0000 C 0x4002_3fff i2c 0 _ba i 2 c 0 interface control registers 0x4003_0000 C 0x4003_3fff spi0_ba spi0 with master/slave function control registers 0x4003_4000 C 0x4003_7fff spi 1 _ba spi 1 with master/slave function control registers 0x4004_0000 C 0x4004_3fff b pwm 0 _ba basic pwm 0 control registers 0x4005_0000 C 0x4005_3fff uart0_ba uart0 control registers 0x400d_0000 C 0x400d_3fff acmp_ba analog comparator control registers 0x400e_0000 C 0x400e_ 3 fff e adc_ba enhanced analog - digital - converter ( e adc) control registers 0x400f_0000 C 0x400f_3fff opa_ba operation amplifier control registers apb2 controllers space (0x4010_0000 ~ 0x401f_ffff) 0x4011_0000 C 0x4011_3fff tmr2 3 _ba timer2 /timer3 control registers 0x4013_0000 C 0x4013_3fff spi 2 _ba spi 2 with master/slave function control registers 0x4015_0000 C 0x4015_3fff uart1_ba uart1 control registers rese rv ed rese rv ed rese rv ed 0x40 19 _0000 C 0x40 19 _3fff epwm0_ba enhanced pwm0 control registers 0x40 19 _ 4 000 C 0x40 19 _ 7 fff epwm1_ba enhanced pwm1 control registers
m0519 nov. 02 , 201 6 page 29 of 69 rev 1 .0 2 m0519 datasheet address space token controllers 0x40 1b _0000 C 0x40 1b _3fff e cap0_ba enhanced input capture 0 control registers 0x40 1b _ 4 000 C 0x40 1b _ 7 fff e cap1_ba enhanced input capture 1 control registers rese rv ed rese rv ed rese rv ed rese rv ed rese rv ed rese rv ed rese rv ed rese rv ed rese rv ed system controllers space (0x e000 _ e 000 ~ 0x e000 _ e fff) 0x e000 _ e 0 1 0 C 0x e000 _ e01 f syst_ba system timer control registers 0x e000 _ e10 0 C 0x e000 _ e4e f nvic_ba external interrupt controller control registers 0x e000 _ ed0 0 C 0x e000 _ ed3 f scs_ba system control registers table 6 - 1 address space assignments for on - chip controllers
m0519 nov. 02 , 201 6 page 30 of 69 rev 1 .0 2 m0519 datasheet 6.2.5 system timer (systick) the cortex ? - m0 includes an integrated system timer, systick, which provides a simple, 24 - bit clear - on - write, decrementing, wrap - on - zero counter with a flexible control mechanism. the counter can be used as a real time operating system (rtos) tick timer or as a simple counter. when system timer is enabled, it will count down from the value in the systick current v alue register (syst_cvr) to 0, and reload (wrap) to the value in the systick reload value register (syst_rvr) on the next clock cycle, then decrement on subsequent clocks. when the counter transitions to 0, the countflag status bit is set. the countflag bi t clears on reads. the syst_cvr value is unknown on reset. software should write to the register to clear it to 0 before enabling the feature. this ensures the timer will count from the syst_rvr value rather than an arbitrary value when it is enabled. if the syst_rvr is 0, the timer will be maintained with a current value of 0 after it is reloaded with this value. this mechanism can be used to disable the feature independently from the timer enable bit. for more detailed information, please refer to th e arm ? cortex ? - m0 technical reference manual and arm ? v6 - m architecture reference manual.
m0519 nov. 02 , 201 6 page 31 of 69 rev 1 .0 2 m0519 datasheet 6.2.6 nested vectored interrupt controller (nvic) the cortex ? - m0 provides an interrupt controller as an integral part of the exception mode, named as nested vectored interrupt controller (nvic), which is closely coupled to the processor core and provides following features: ? nested and vectored interrupt support ? au tomatic processor state saving and restoration ? reduced and deterministic interrupt latency the nvic prioritizes and handles all supported exceptions. all exceptions are handled in handler mode. this nvic architecture supports 32 (irq[31:0]) discrete inte rrupts with 4 levels of priority. all of the interrupts and most of the system exceptions can be configured to different priority levels. when an interrupt occurs, the nvic will compare the priority of the new interrupt to the current running ones priorit y. if the priority of the new interrupt is higher than the current one, the new interrupt handler will override the current handler. when an interrupt is accepted, the starting address of the interrupt service routine (isr) is fetched from a vector table i n memory. there is no need to determine which interrupt is accepted and branch to the starting address of the correlated isr by software. while the starting address is fetched, nvic will also automatically save processor state including the registers pc, psr, lr, r0~r3, r12 to the stack. at the end of the isr, the nvic will restore the mentioned registers from stack and resume the normal execution. thus it will take less and deterministic time to process the interrupt request. the nvic supports tail chai ning which handles back - to - back interrupts efficiently without the overhead of states saving and restoration and therefore reduces delay time in switching to pending isr at the end of current isr. the nvic also supports late arrival which improves the e fficiency of concurrent isrs. when a higher priority interrupt request occurs before the current isr starts to execute (at the stage of state saving and starting address fetching), the nvic will give priority to the higher one without delay penalty. thus i t advances the real - time capability. for more detailed information, please refer to the arm ? cortex ? - m0 technical reference manual and arm ? v6 - m architecture reference manual.
m0519 nov. 02 , 201 6 page 32 of 69 rev 1 .0 2 m0519 datasheet exception model and system interrupt map 6.2.6.1 table 6 - 2 lists the exception model supported by the numicro ? m0519 series . software can set four levels of priority on some of these exceptions as well as on all interrupts. the highest user - configurable priority is denoted as 0 and the lowest priority is denoted as 3. the default priority of all the user - configurable interrupts is 0. note that priority 0 is treated as the fourth priority on the system, after three system exceptions reset, nmi and hard fault. exception name vector number priority reset 1 - 3 nmi 2 - 2 hard fault 3 - 1 reserved 4 ~ 10 reserved svcall 11 configurable reserved 12 ~ 13 reserved pendsv 14 configurable systick 15 configurable interrupt (irq0 ~ irq31) 16 ~ 47 configurable table 6 - 2 exception model exception number vector address interrupt number ( bit i n interrupt registers ) interrupt name source module exception d escription power down w ake - u p 1 ~ 15 - - - system exceptions - 16 0x40 0 bod_ int brown - o ut brown - o ut low voltage detected interrupt yes 17 0x44 1 wdt_int wdt watch d og timer interrupt yes 18 0x48 2 e int0 _int p3.2 external signal interrupt from p3.2 pin yes 19 0x4c 3 e int1 _int p3.3 external signal interrupt from p3.3 pin yes 20 0x50 4 gp g0 _int p0~p4 except p3.2 and p3.3 external interrupt from gpio group 0 (p0~p4) except p3.2 and p3.3 yes 21 0x54 5 gp g1 _int p5~pa external interrupt from gpio group 1 (p5~pa) yes 22 0x58 6 b pwm 0 _int b pwm 0 basic pwm0 interrupt no 23 0x5c 7 e adc 0 _int e adc 0 e adc 0 interrupt no 24 0x60 8 tmr0_int tmr0 timer 0 interrupt no 25 0x64 9 tmr1_int tmr1 timer 1 interrupt no 26 0x68 10 tmr2_int tmr2 timer 2 interrupt no 27 0x6c 11 tmr3_int tmr3 timer 3 interrupt no 28 0x70 12 uart0_int uart0 uart0 interrupt yes
m0519 nov. 02 , 201 6 page 33 of 69 rev 1 .0 2 m0519 datasheet exception number vector address interrupt number ( bit i n interrupt registers ) interrupt name source module exception d escription power down w ake - u p 29 0x74 13 uart1_int uart1 uart1 interrupt yes 30 0x78 14 spi0_int spi0 spi0 interrupt no 31 0x7c 15 spi1_int spi1 spi1 interrupt no 32 0x 8 0 16 spi2_int spi2 spi2 interrupt no 33 0x84 17 reserved reserved reserved - 33 0x 8 4 17 reserved reserved reserved no 34 0x 8 8 18 i2c 0 _int i 2 c 0 i 2 c 0 interrupt yes 35 0x 8 c 19 ckd_int ckd ckd interrupt no 36 0x90 20 reserved reserved reserved - 36 0x 9 0 20 reserved reserved reserved - 37 0x 9 4 21 epwm0_int epwm0 enhanced pwm0 interrupt no 38 0x 9 8 22 epwm1_int epwm1 enhanced pwm1 interrupt no 39 0x 9 c 23 e cap0_int e cap0 enhanced i nput capture 0 interrupt no 40 0x a 0 24 e cap1_int e cap1 enhanced i nput capture 1 interrupt no 41 0x a 4 25 acmp_int a cmp analog comparator 0 or 1 , or op amplifier digital output interrupt yes (only by analog comparator) 42 0xa8 26 reserved reserved reserved - 43 0xac 27 reserved reserved reserved - 42 0x a 8 26 reserved reserved reserved - 43 0x a c 27 reserved reserved reserved - 44 0x b 0 28 pwrwu_int clkc clock controller interrupt for chip wake up from power - down state - 45 0x b 4 29 e adc 1 _int e adc 1 e adc 1 interrupt no 46 0x b 8 30 e adc 2 _int e adc 2 e adc 2 interrupt no 47 0x b c 31 e adc 3 _int e adc 3 e adc 3 interrupt no table 6 - 3 system interrupt map vector table
m0519 nov. 02 , 201 6 page 34 of 69 rev 1 .0 2 m0519 datasheet vector table 6.2.6.2 when an interrupt is accepted, the processor will automatically fetch the starting address of the interrupt service routine (isr) from a vector table in memory. for armv6 - m, the vector table base address is fixed at 0x00000000. the vector table contains the initialization value for the stack pointer on reset, and the entry point addresses for all exception handlers. the vector number on pre vious page defines the order of entries in the vector table associated with exception handler entry as illustrated in previous section. vector table word offset ( bytes ) description 0 sp_main C the main stack pointer vector number exception entry pointer using that vector number table 6 - 4 vector table operation description 6.2.6.3 nvic interrupts can be enabled and disabled by writing to their corresponding interrupt set - enable or interrupt clear - enable register bi t - field. the registers use a write - 1 - to - enable and write - 1 - to - clear policy, both registers reading back the current enabled state of the corresponding interrupts. when an interrupt is disabled, interrupt assertion will cause the interrupt to become pending , however, the interrupt will not be activated. if an interrupt is active when it is disabled, it remains in its active state until cleared by reset or an exception return. clearing the enable bit prevents new activations of the associated interrupt. nvic interrupts can be pended/un - pended using a complementary pair of registers to those used to enable/disable the interrupts, named the set - pending register and clear - pending register respectively. the registers use a write - 1 - to - enable and write - 1 - to - clear po licy, both registers reading back the current pended state of the corresponding interrupts. the clear - pending register has no effect on the execution status of an active interrupt. nvic interrupts are prioritized by updating an 8 - bit field within a 32 - bit register (each register supporting four interrupts). the general registers associated with the nvic are all accessible from a block of memory in the system control space and will be described in next section.
m0519 nov. 02 , 201 6 page 35 of 69 rev 1 .0 2 m0519 datasheet c lock c ontroller 6.3 6.3.1 overview the clock controller generates the clock s for the whole chip , includ ing system clocks and all peripheral clocks . the clock controller also implements the power control function with the individually clock on/off control, clock source select ion and clock divider . the chip enters p ower - d ow n mode when cortex ? - m0 core execute s the wfi i nstruction only if the sleepdeep (scr[2]) bit is set to 1 . after that, chip enter s power - down mode and wait for wake - up interrupt source triggered to leave power - down mode. in the power - down mode, the clock controller turns off the 4~24 mhz external high speed crystal oscillator and 22.1184 mhz internal high speed rc oscillator to reduce the overall system power consumption. figure 6 - 3 show s the clock generator and the overview of the clock source control. the clock generator consists of 4 clock sources as listed below: ? 4~24 mhz external high speed crystal oscillator (hxt) ? p rogrammable pll output clock frequency (pll_fout), pll source can be selected from 4~24 mhz external high speed crystal oscillator (hxt) or 22.1184 mhz internal high speed rc oscillator (hirc) ? 22.1184 mhz i nternal high speed rc oscillator (hirc) ? 10 khz internal low sp eed rc oscillator (lirc) each of these clock sources has certain stable time to wait for clock operating at stable frequency. when clock source is enabled, a stable counter start counting and correlated clock stable index (osc22m_stb(clkstatus[4]), osc10k _stb(clkstatus[3]), pll_stb(clkstatus[2]) and xtl12m_stb(clkstatus[0])) are set to 1 after stable counter value reach a define value as table 6 - 5 . system and peripheral can use these clock as its operating clock only when correlate clock stable index is set to 1. the clock stable index will auto clear when user disables the clock source (osc10k_en(pwrcon[3]), osc22m_en(pwrcon[2]), xtl12m_en(pwrcon[0] ) and pd(pllcon[16])). besides, the clock stable index of hxt, hirc and pll will auto clear when chip enter power - down and clock stable counter will re - counting after chip wake - up if correlate clock is enabled. clock source clock stable c ount value hxt 4096 hxt clock pll 6144 pll source (pll source is hxt if pll_src(pllcon[19]) = 0, or hirc if pll_src(pllcon[19]) = 1) hirc 256 hirc clock lirc 1 lirc table 6 - 5 clock stable count value table
m0519 nov. 02 , 201 6 page 36 of 69 rev 1 .0 2 m0519 datasheet figure 6 - 3 clock generator block diagram x t 1 _ i n 4 ~ 2 4 m h z h x t x t l 1 2 m _ e n ( p w r c o n [ 0 ] ) x t 1 _ o u t 2 2 . 1 1 8 4 m h z h i r c o s c 2 2 m _ e n ( p w r c o n [ 2 ] ) 0 1 p l l p l l _ s r c ( p l l c o n [ 1 9 ] ) p l l f o u t 1 0 k h z l i r c o s c 1 0 k _ e n ( p w r c o n [ 3 ] ) h x t h i r c l i r c l e g e n d : h x t = 4 ~ 2 4 m h z e x t e r n a l h i g h s p e e d c r y s t a l o s c i l l a t o r h i r c = 2 2 . 1 1 8 4 m h z i n t e r n a l h i g h s p e e d r c o s c i l l a t o r l i r c = 1 0 k h z i n t e r n a l l o w s p e e d r c o s c i l l a t o r
m0519 nov. 02 , 201 6 page 37 of 69 rev 1 .0 2 m0519 datasheet figure 6 - 4 clock g enerator g lobal v iew d iagram 1 0 p l l c o n [ 1 9 ] 2 2 . 1 1 8 4 m h z 4 ~ 1 2 m h z p l l f o u t 1 1 1 0 1 1 0 1 0 0 0 1 4 ~ 2 4 m h z r e s e r v e d 4 ~ 2 4 m h z h c l k 2 2 . 1 1 8 4 m h z 0 0 0 1 / 2 1 / 2 1 / 2 c l k s e l 0 [ 5 : 3 ] 1 0 s y s t i c k t m r 3 e a d c u a r t 0 - 1 a c m p i 2 c w d t t m r 0 t m r 1 t m r 2 c p u f m c 1 0 k h z 1 1 1 0 1 1 0 1 0 0 0 1 p l l f o u t r e s e r v e d 4 ~ 2 4 m h z 1 0 k h z 2 2 . 1 1 8 4 m h z 0 0 0 c l k s e l 0 [ 2 : 0 ] s y s t _ c s r [ 2 ] c p u c l k 1 / ( h c l k _ n + 1 ) p c l k c p u c l k h c l k 2 2 . 1 1 8 4 m h z w w d t 1 0 k h z 1 / ( e a d c _ n + 1 ) 1 1 1 0 c l k s e l 1 [ 1 : 0 ] h c l k 1 / 2 0 4 8 1 / ( u a r t _ n + 1 ) 2 2 . 1 1 8 4 m h z 4 ~ 2 4 m h z 0 1 1 1 0 1 0 0 p l l f o u t 4 ~ 2 4 m h z 2 2 . 1 1 8 4 m h z c l k s e l 1 [ 2 5 : 2 4 ] 1 0 s p i 0 c l k s e l 1 [ 4 ] c l k s e l 1 [ 5 ] c l k s e l 1 [ 6 ] h c l k 1 1 1 0 0 1 0 0 h c l k 4 ~ 2 4 m h z 2 2 . 1 1 8 4 m h z r e s e r v e d c l k s e l 2 [ 3 : 2 ] f r q d i v b o d 1 0 k h z 1 1 1 0 c l k s e l 2 [ 1 7 : 1 6 ] 1 0 k h z 0 0 h c l k 1 / 5 1 2 h c l k 1 / 1 2 8 p c l k e p w m 1 b p w m 0 e p w m 0 s p i 1 s p i 2 p l l f o u t o p a e c a p 0 e c a p 1 m d u q e i 0 q e i 1 n o t e : b e f o r e c l o c k s w i t c h i n g , b o t h t h e p r e - s e l e c t e d a n d n e w l y s e l e c t e d c l o c k s o u r c e s m u s t b e t u r n e d o n a n d s t a b l e .
m0519 nov. 02 , 201 6 page 38 of 69 rev 1 .0 2 m0519 datasheet flash memory controller (fmc) 6.4 6.4.1 overview the numicro ? m0519 series is equipped with 128/64 k b on - chip embedded f lash for application program memory (aprom) and data flash , and with 8 k bytes for isp loader program memory (ldrom) that could be programmed boot loader to update aprom and d ata f lash through in system programming (isp) procedure. isp function enables user to update embedded flash when chip is soldered on pcb. after chip is powered on, cortex ? - m0 cpu fetches code from aprom or ldrom decided by boot select cbs ( config0 [7:6] ) . by the way, the numicro ? m0519 series also provides data f lash for user to store some application dependent data before chip power off . for 128 k b aprom device, the data flash is shared with original 128 k b program memory and its start address is configurable in config1. for 64 k b aprom device, the data flash is fixed at 4k bytes . 6.4.2 features ? run s up to 72 mhz and optional up to 50 mhz with zero wait state for continuous address read access ? supp orts 512 bytes page erase for all embedded flash ? supports 128/64 k bytes application program rom (aprom) ? supports 8 kb loader rom (ldrom) ? supports 4kb d ata f lash for 64 k bytes aprom device ? supports c onfigu rable data flash size for 128kb aprom device ? supports 8 bytes user configuration block to control system initiation ? support in - syste m - program ming (isp) / in - application - programming (iap) to update embedded flash memory
m0519 nov. 02 , 201 6 page 39 of 69 rev 1 .0 2 m0519 datasheet g eneral purpose i/o (gpio) 6.5 6.5.1 overview the numicro ? m0519 series has up to 82 general purpose i/o pins to be shared with other function pins depending on the chip configuration. these 82 pins are arranged in 10 ports named as p0, p1, p2, p3, p4, p5, p6, p7, p8, p9 and pa. the p0/1/2/3/4/5/6/7/8/9 port has the ma ximum of 8 pins and pa port has the maximum of 2 pins. each of the 82 pins is independent and has the corresponding register bits to control the pin mode function and data. the i/o type of each of i/o pins can be configured by software individually as inpu t, output, open - drain or quasi - bidirectional mode. after reset, the i/o mode of all pins are stay at input mode. in quasi - bidirectional mode, i/o pin has a very weak individual pull - up resistor which is about 110~300 k ? for v dd is from 5.0 v to 2.5 v. 6.5.2 features ? four i/o modes: ? quasi - b i d irectional ? push - pull output ? open - drain output ? input only with high impendence ? ttl/schmitt trigger input selectable by px_type[7:0] in px_mfp[23:16] ? i/o pin configu red as interrupt source with edge/level setting ? i/o pin internal pull - up resistor enabled only in quasi - bidirectional i/o mode ? enabling pin interrup t function will also enable the pin wake - up function
m0519 nov. 02 , 201 6 page 40 of 69 rev 1 .0 2 m0519 datasheet t imer controller (timer) 6.6 6.6.1 overview the timer c ontroller includes four 32 - bit timers, t imer 0 ~ t imer 3, allowing user to easily implement a timer control for applications. the timer can perform functions, such as frequency measurement, delay timing, clock generation, and event counting by external input pins, and interval measurement by external capture pins . 6.6.2 featu res ? four sets of 32 - bit timers with 24 - bit up counter and one 8 - bit prescale counter ? independent clock source for each timer ? provides one - shot, periodic, toggle - output and continuous counting operation modes ? 24 - bit up counter value is readable through tdr (tdr[23:0]) ? supports event counting function ? supports external capture pin event for interval measurement ? supports exter nal capture pin event to reset 24 - bit up counter
m0519 nov. 02 , 201 6 page 41 of 69 rev 1 .0 2 m0519 datasheet b asic pwm g enerator and c apture t imer (bpwm) 6.7 6.7.1 overview the numicro ? m0519 series has 1 set of b pwm group (bpwm0), support ing 1 set of b pwm g enerators that can be configured as 2 independent b pwm outputs, b pwm 0 _ch 0 and b pwm 0 _ch 1 , or as 1 complementary b pwm pairs, ( b pwm 0_ch0 , b pwm 0_ch 1) with programmable d ead - zone generator. the b pwm g enerator has one 8 - bit prescal e r, one clock divider with 5 divided frequencies (1, 1/2, 1/4, 1/8, 1/16), two b pwm timers including two clock selectors, two 16 - bit b pwm down - counters for b pwm period control, two 16 - bit comparators for b pwm duty control and one dead - zone generator. the b pwm g enerator provide s two independent b pwm interrupt flags which are set by hardware when the corresponding b pwm period down counter reaches zero. each b pwm interrupt source with its corresponding enable bit can cause cpu to request b pwm interrupt. the b pwm generators can be configured as one - shot mode to produce only one b pwm cycle signal or auto - reload mode to output b pwm waveform continuously. b pwm can be used to trigger e adc when operation in center - aligned mode. 6.7.2 features b pwm function: 6.7.2.1 ? up to 1 b pwm group to support 2 b pwm channels or 1 b pwm paired channels . ? supports 8 - bit prescaler from 1 to 255 ? up to 16 - bit resolution b pwm timer ? pwm timer supports edge - aligned and center - aligned operation type ? one - shot or auto - reload mode b pwm ? pwm interrupt request synchronized with b pwm period or duty ? supports dead - zone generator with 8 - bit resolution for b pwm paired channels ? supports tri gger e adc capture function: 6.7.2.2 ? suppor ts 2 capture input channels shared with 2 b pwm output channels ? supports rising or falling capture condition ? suppor ts rising or falling capture interrupt
m0519 nov. 02 , 201 6 page 42 of 69 rev 1 .0 2 m0519 datasheet enhanced pwm generator (epwm) 6.8 6.8.1 overview this device has two buil t - in pwm units with the same architecture whose function is specially designed for driv ing motor control applications. 6.8.2 features each unit supports the features below : ? three independent 16 - bit pwm duty control units with maximum 6 port pins: ? 3 independent pwm output: e pwm0 _ch 0, e pwm0 _ch 2 and e pwm0 _ch 4 for unit 0 e pwm1 _ch 0, e pwm1 _ch 2 and e pwm1 _ch 4 for unit 1 ? 3 complementary pwm pairs, with each pin in a pair mutually complement to each other and capable of programmable dead - time insertion: ( e pwmx _ch 0, e pwmx _ch 1), (pwmx _ch 2, e pwmx _ch 3) and ( e pwmx _ch 4, e pwmx _ch 5) where x=0~1. ? 3 synchronous pwm pairs, with each pin in a pair in - phase: ( e pwmx _ch 0, e pwmx _ch 1), ( e pwmx _ch 2, e pwmx _ch 3) and ( e pwmx _ch 4, e pwmx _ch 5) where x=0~1 ? group c ontrol bits: epwmx_ch2 and epwmx_ch4 are synchronized with epwmx_ch0 ? supports edge aligned mode and center aligned mode ? programmable dead - time insertion between complementary paired pwms ? each pin of epwmx_ch0 to epwmx_ch5 has independent polarity setting control ? mask output control for electrically commutated moto r operation ? tri - state output at reset and brake state ? hardware brake protection ? two interr upt source s : ? interrupt is synchronously requested at pwm frequency when up/down counter comparison matched (edge and center aligned modes) or underflow (center aligne d mode). ? interrupt is requested when external brake pins asserted ? pwm signals bef ore polarity control stage are defined in the view of positive logic. the pwm ports is active high or active low are controlled by polarity control register. ? high source/sink current. ? supports trigge r eadc
m0519 nov. 02 , 201 6 page 43 of 69 rev 1 .0 2 m0519 datasheet e nhanced i nput c apture t imer (ecap) 6.9 6.9.1 overview this device provides up to two units of input capture timer/counter which capture function can detect the digital edge changed signal at channel inputs. each unit has three input capture channels. the timer/counter is equipped with up counting, reload and compare - match capabilities. 6.9.2 features ? up to two input capture timer/counter units, input capture 0 and input capture 1. ? each unit has own interrupt vector ? 24 - bit input captu re up - counting timer/counter ? with noise filter in front end of input ports ? edge detector with t hree options ? risi ng edge detection ? falling edge detection ? both edge detection ? each i nput channel is supported with one capture counter hold register ? captured eve nt reset/reload capture counter option ? support s the compare - match function
m0519 nov. 02 , 201 6 page 44 of 69 rev 1 .0 2 m0519 datasheet w atchdog t imer (wdt) 6.10 6.10.1 overview the purpose of watchdog timer (wdt) is to perform a system reset when system runs into an unknown state. this prevents system from hanging for an infinite period of time. besides, this watchdog timer supports the function to wake - up system from idle/power - down mode. 6.10.2 features ? 18 - bit free running up counter for wdt time - out interval ? selectable time - out interval (2 4 ~ 2 18 ) and the time - out interval is 1.6 ms ~ 26. 214 s if wdt_clk = 10 khz ? syste m kept in reset state for a period of (1 / wdt_clk) * 63 ? supports selectable wdt reset delay period, including 1026 130 18 or 3 wdt_clk reset delay period ? supports to force wdt enabled after chip powered on or reset by setting cwdten in config0 register ? support s wdt time - out wake - up function only if wdt clock source is selected as 10 k hz
m0519 nov. 02 , 201 6 page 45 of 69 rev 1 .0 2 m0519 datasheet window watchdog timer (wwdt) 6.11 6.11.1 overview the window watchdog timer is used to perform a system reset within a specified window period to prevent software from run n ing to uncontrollable stat e by any unpredictable condition usually generated by external interferences or unexpected logical conditions . when the window function is used to trim the watchdog behavior to match the application perfectly, software must refresh the counter before time - out. 6.11.2 features ? 6 - bit down counter value wwdtcval (wwdtcvr[5:0] ) and 6 - bit compare value wincmp (wwdtcr[21:16]) to make the wwdt time - out window period flexible ? supports 4 - bit value p eriod sel (wwdtcr[11:8]) to programmable maximum 11 - bit prescale counter period of wwdt counter ? wwdt counter suspends in i dle/power - down mode
m0519 nov. 02 , 201 6 page 46 of 69 rev 1 .0 2 m0519 datasheet u niversal a synchronous r eceiver t ransmitter (uart) 6.12 6.12.1 overview the numicro ? m0519 series provide s two channels of universal asynchronous receiver/transmitters (uart). uart control ler performs normal speed uart and support s flow control function. the uart controller performs a serial - to - parallel conversion on da ta received from the peripheral and a parallel - to - serial conversion on data transmitted from the cpu. each uart controller channel supports seven types of int errupts. the uart c ontroller also supports irda si r , rs - 485 and lin . 6.12.2 features ? fu ll duplex, asynchronous communications ? separates receive / transmit 16 bytes entry fifo for data payloads ? supports hardware auto - flow control/flow control function (ncts, nrts) and programmable nrts flow control trigger level ? programmable receiver buffer trigger level ? supports programmable baud - rate generator for each channel individually ? supports ncts wake - up function ? supports 8 - bit receiver buffer time out detection funct ion ? programmable transmitting data delay time between the last stop and the next start bit by setting dly (ua_tor [15:8]) register ? supports break error, frame error, parity error and receive / transmit buffer overflow detect function ? fully programm able ser ial - interface characteristics ? programmable data bit length , 5 - , 6 - , 7 - , 8 - bit character ? programmable parity bit, even, odd, no parity or stick parity bit generation and detection ? programmable stop bit length , 1, 1.5, or 2 stop bit generation ? irda sir function mode ? support s 3 - /16 - bit duration for normal mode ? lin function mode ? support s lin master/ s lave mode ? support s programmable break generation function for transmitter ? support s break detect function for receiver ? rs - 485 function mode ? support s rs - 485 9 - bi t mode ? support s hardware or software direct enable control provided by n rts pi n
m0519 nov. 02 , 201 6 page 47 of 69 rev 1 .0 2 m0519 datasheet i 2 c s erial interface controller ( i2c ) 6.13 6.13.1 overview i 2 c is a two - wire, bi - directional serial bus that provides a simple and efficient method of data exchange between devices. the i 2 c standard is a true multi - master bus including collision detection and arbitration that prevents data corruption if two or more masters attempt to control the bus simultaneously. i 2 c controller supports power - down wake - up function . 6.13.2 features the i 2 c bus uses two wires (sda and scl) to transfer information between devices connected to the bus. the main features of the bus are: ? master/ slave mode ? bidirectional data transfer between masters and slaves ? multi - master bus (no central master) ? arbitration between simultaneously transmitting masters without corruption of serial data on the bus ? serial clock synchronization allows devices with different bit rates to communicate via one serial bus ? serial clock synchronization can be used as a handshake mechanism to sus pend and resume serial transfer ? a b uilt - in a 14 - bit time out counter request ed the i 2 c interrupt if the i 2 c bus hangs up and timer - out counter overflows. ? extern al pull - up resistors are needed for high output ? programmable clocks allow versatile rate contro l ? supports 7 - bit addressing mode ? supports multiple address recognition ( f our slave address with mask option)
m0519 nov. 02 , 201 6 page 48 of 69 rev 1 .0 2 m0519 datasheet s erial p eripheral i nterface (spi) 6.14 6.14.1 overview the serial peripheral interface ( spi ) is a synchronous serial data communication protocol that operates in full duplex mode. devices communicate in master/slave mode with the 4 - wire bi - direction interface. the numicro ? m0519 series contains up to three sets of spi controller s perform ing a serial - to - parallel conversion on data received from a periphe ral device , and a parallel - to - serial conversion on data transmitted to a peripheral device . each set of spi controller can be configured as a master or a slave device . 6.14.2 features ? up to three sets of spi controller s ? supports master or slave mode operation ? configurable bit length of a trans action word from 8 to 32 - bit ? provides separate 8 - layer depth transmit and receive fifo buffers ? supports msb first or lsb first transfer sequence ? supports the b yte r eorder function ? supports 3 - w ire, no slave select signal, bi - direction interface
m0519 nov. 02 , 201 6 page 49 of 69 rev 1 .0 2 m0519 datasheet hardware divider (hdiv) 6.15 6.15.1 overview the hardware divider is useful to the high performance application. the hardware divider is a signed, integer divider with quotient and remainder outputs. 6.15.2 features ? supports si gned (twos complement) integer calculation. ? supports 32 - bit dividend with 16 - bit divisor calculation capacity. ? supports 32 - bit quotient and 16 - bit remainder outputs. ? supports d ivided by 0 warning flag. ? 7 hclk clocks taken for one cycle calculation. ? software triggered with finish flag.
m0519 nov. 02 , 201 6 page 50 of 69 rev 1 .0 2 m0519 datasheet enhanced a nalog - to - d igital c onverter ( e adc) 6.16 6.16.1 overview the numicro ? m0519 series contains two 12 - bit successive approximation analog - to - digital converters (sar a/d converter) with 16 input channels. the two a/d converters adca and adcb can be sampled with simultaneous or single sampling mode. the a/d converters can be started by softw are, pwm triggers, timer0~3 overflow pulse triggers, adint0, adint1 interrupt eoc pulse trigger and external stadc pin input signal. note: the analog input port pins must be configured as input type before the e adc function is enabled. 6.16.2 features ? analog inp ut voltage range: 0~v ref (max to 5.0v). ? 12 - b it resolution and 10 - bit accuracy is guaranteed. ? up to 16 single - end analog input channels. ? two sar adc converters. ? four e adc interrupts with individual interrupt vector addresses. ? maximum e adc clock frequency : 16mhz. ? up to 1.6m sps conversion rate, each of adc converter conversion time less than 1.25s. ? two operatin g modes ? single sampling mode: two adc converters run at normal operation . ? simultaneous sampling mode: allow two adc converters can be sampled simulta neously. ? an a/d conversion can be started by : ? writing 1 to adst (adsstr[n]) bit ( n = 0~15) through software ? external pin stadc ? timer0 ~3 overflow pulse triggers ? adint0, adint1 interrupt eoc pulse triggers ? pwm triggers ? conver sion results are held in 16 data registers with valid and overrun indicators. ? samplea0~7 adc control logic modules, each of them is configurable for adca converter channel aina0~7 and trigger source. ? sampleb0~7 adc control logic modules, each of them is configurable for adcb converte r channel ainb0~7 and trigger source. ? channel aina0 supports 2 input sources: external analog voltage and internal op0 amplifier output voltage. ? channel ainb0 supports 2 input sources: external analog voltage and internal op1 amplifier output voltage. ? channel aina7 supports 4 input sources: external analog voltage, internal fixed band - gap voltage, intern al temperature sensor output , and analog ground.
m0519 nov. 02 , 201 6 page 51 of 69 rev 1 .0 2 m0519 datasheet a nalog c omparator (acmp) 6.17 6.17.1 overview the numicro ? m0519 series contains three comparators. the comparator output is logic 1 when positive input voltage is greater than negative input voltage ; otherwise the output is logic 0 . each comparator can be configured to cause an interrupt when the comparator output value changes. the block diagram is shown in e` ! ??? . 6.17.2 features ? analog input voltage range: 0~ a v dd ? su pports hysteresis function ? supports wake - up function ? supports comparator output inverse function ? supports the comparator output can be the brake source for epwm function ? acmp0 supports ? 2 positive sources : acmp0 _p and op0_o ? 2 negative sources: acmp0_n and internal band - gap voltage (v bg ) ? acmp1 supports ? 2 positive sources : acmp 1 _p and op 1 _o ? 2 negative sources : acmp 1 _n and internal band - gap voltage ( v bg ) ? acmp2 supports ? 1 positive sources : acmp 2 _p ? 2 negative sources : acmp 2 _n and internal band - gap voltage ( v bg ) ? share s one acmp interrupt vector for all comparators
m0519 nov. 02 , 201 6 page 52 of 69 rev 1 .0 2 m0519 datasheet o p a mplifier (opa) 6.18 6.18.1 overview this device integrated two operational amplifier s . it can be enabled through op 0 _en (opacr[0]) and op1_en (opacr[1]) bit. user can measure the output of the op amplifier through the integrated a/d convert er . 6.18.2 features ? analog input voltage range: 0~ a v dd ? supports t wo analog op amplifiers ? supports op output voltage measurement by a/d converter ? supports s chmitt trigger buffer outputs and generate interrupt ? op amplifier 0 output can be an optional input source of integrated comparator 0 positive input ? op amplifier 1 output can be an optional input source of integrated comparator 1 positive input
m0519 nov. 02 , 201 6 page 53 of 69 rev 1 .0 2 m0519 datasheet 7 electrical character istics absolute maximum ratings 7.1 symbol parameter min max unit dc power supply v dd ? v ss - 0.3 + 6.3 v input voltage v in v ss - 0.3 v dd +0.3 v oscillator frequency 1/t clcl 4 24 mhz operating temperature ta - 40 105 ? c storage temperature t st - 55 +150 ? c maximum current into vdd - 120 ma maximum current out of vss 120 ma maximum current sunk by a i/o pin 35 ma maximum current sourced by a i/o pin 35 ma maximum current sunk by total i/o pins 100 ma maximum current sourced by total i/o pins 100 ma note: exposure to conditions beyond those listed under absolute maximum ratings may adversely affects the lift and reliability of the device.
m0519 nov. 02 , 201 6 page 54 of 69 rev 1 .0 2 m0519 datasheet dc electrical characteristics 7.2 parameter sym . specification test conditions min. typ. max. unit operation voltage v dd 2.5 - 5.5 v v dd =2.5v ~ 5.5v power ground v ss / av ss - 0.3 - - v ldo output voltage v ldo 1.62 1.8 1.98 v v dd > = 2. 5 v analog operating voltage av dd 2.5 - v dd v analog reference voltage v ref 1.2 - av dd v operating current normal run mode a t 72mhz while(1){} executed from flash v ldo =1.8v i dd1 38. 7 ma vdd hxt hirc pll all digital module 5.5v 12mhz ? ? i dd2 17. 9 ma 5.5v 12mhz ? i dd3 37. 2 ma 3.3v 12mhz ? ? i dd4 16. 4 ma 3.3v 12mhz ? operating current normal run mode a t 60mhz while(1){} executed from flash v ldo =1.8v i dd5 32. 9 ma 5.5v 12mhz ? ? i dd6 15. 5 ma 5.5v 12mhz ? i dd7 31. 4 ma 3.3v 12mhz ? ? i dd 8 14.0 ma 3.3v 12mhz ? operating current normal run mode a t 50mhz while(1){} executed from flash v ldo =1.8v i dd 9 29 .1 ma 5.5v 12mhz ? ? i dd 10 14. 5 ma 5.5v 12mhz ? i dd 11 27. 6 ma 3.3v 12mhz ? ? i dd 12 13.0 ma 3.3v 12mhz ? operating current normal run mode a t 48mhz while(1){} executed from flash v ldo =1.8v i dd 13 28. 1 ma 5.5v 12mhz ? ? i dd 14 14.0 ma 5.5v 12mhz ? i dd 15 26. 6 ma 3.3v 12mhz ? ? i dd 16 12. 5 ma 3.3v 12mhz ? operating current normal run mode a t 32mhz while(1){} executed from flash v ldo =1.8v i dd 17 19. 9 ma 5.5v 12mhz ? ? i dd 18 10. 4 ma 5.5v 12mhz ? i dd 19 18. 4 ma 3.3v 12mhz ? ? i dd 20 8. 9 ma 3.3v 12mhz ?
m0519 nov. 02 , 201 6 page 55 of 69 rev 1 .0 2 m0519 datasheet parameter sym . specification test conditions min. typ. max. unit operating current normal run mode a t 22.1184mhz while(1){} executed from flash v ldo =1.8v i dd 21 11. 7 ma 5.5v ? ? i dd 22 5. 3 ma 5.5v ? i dd 23 11. 6 ma 3.3v ? ? i dd 24 5. 2 ma 3.3v ? operating current normal run mode a t 12mhz while(1){} executed from flash v ldo =1.8v i dd 25 8.6 ma 5.5v 12mhz ? i dd 26 4. 9 ma 5.5v 12mhz i dd 27 7. 2 ma 3.3v 12mhz ? i dd 28 3. 4 ma 3.3v 12mhz operating current normal run mode a t 10khz while(1){} executed from flash v ldo =1.8v i dd 29 0.1 3 ma vdd hxt/ lxt lirc pll all digital module 5.5v 10khz ? i dd 30 0.1 2 ma 5.5v 10khz i dd 31 0.1 1 ma 3.3v 10khz ? i dd 32 0.1 1 ma 3.3v 10khz operating current idle mode a t 72mhz while(1){} executed from flash v ldo =1.8v i idle1 30. 1 ma vdd hxt hirc pll all digital module 5.5v 12mhz ? ? i idle2 9. 2 ma 5.5v 12mhz ? i idle3 28. 6 ma 3.3v 12mhz ? ? i idle4 7. 7 ma 3.3v 12mhz ? operating current idle mode a t 60mhz while(1){} executed from flash v ldo =1.8v i idle5 25. 7 ma 5.5v 12mhz ? ? i idle6 8. 2 ma 5.5v 12mhz ? i idle7 24. 2 ma 3.3v 12mhz ? ? i idle8 6. 7 ma 3.3v 12mhz ? operating current idle mode a t 50mhz while(1){} executed from flash v ldo =1.8v i idle9 2 3.0 ma 5.5v 12mhz ? ? i idle10 8. 4 ma 5.5v 12mhz ? i idle11 21. 5 ma 3.3v 12mhz ? ? i idle12 6. 9 ma 3.3v 12mhz ?
m0519 nov. 02 , 201 6 page 56 of 69 rev 1 .0 2 m0519 datasheet parameter sym . specification test conditions min. typ. max. unit operating current idle mode a t 48mhz while(1){} executed from flash v ldo =1.8v i idle13 22. 3 ma 5.5v 12mhz ? ? i idle14 8. 1 ma 5.5v 12mhz ? i idle15 20. 8 ma 3.3v 12mhz ? ? i idle16 6. 7 ma 3.3v 12mhz ? operating current idle mode a t 32mhz while(1){} executed from flash v ldo =1.8v i idle17 1 6.0 ma 5.5v 12mhz ? ? i idle18 6. 4 ma 5.5v 12mhz ? i idle19 14. 5 ma 3.3v 12mhz ? ? i idle20 4. 9 ma 3.3v 12mhz ? operating current idle mode a t 22.1184mhz while(1){} executed from flash v ldo =1.8v i idle21 8. 6 ma 5.5v ? ? i idle22 2. 2 ma 5.5v ? i idle23 8. 6 ma 3.3v ? ? i idle24 2. 2 ma 3.3v ? operating current idle mode a t 12mhz while(1){} executed from flash v ldo =1.8v i idle25 7. 2 ma 5.5v 12mhz ? i idle26 3. 4 ma 5.5v 12mhz i idle27 5. 7 ma 3.3v 12mhz ? i idle28 1.9 ma 3.3v 12mhz operating current idle mode a t 10khz while(1){} executed from flash v ldo =1.8v i idle29 0.1 3 ma vdd hxt/ lxt lirc pll all digital module 5.5v 10khz ? i idle30 0.1 2 ma 5.5v 10khz i idle31 0.1 1 ma 3.3v 10khz ? i idle32 0.1 1 ma 3.3v 10khz standby current power - down mod e i pwd 1 - ? a vdd hxt hirc lirc all digital module 5.5v ? i pwd 2 - ? a 5.5v ? i pwd 3 - ? a 5.5v ? i pwd 4 - ? a 3.3v ? i pwd 5 - ? a 3.3v ?
m0519 nov. 02 , 201 6 page 57 of 69 rev 1 .0 2 m0519 datasheet parameter sym . specification test conditions min. typ. max. unit i pwd 6 - ? a 3.3v ? logic 0 input current (quasi - bidirectional mode) i i l - - - 75 ? a input leakage current (input only) i lk - - 2 ? a logic 1 to 0 transition current (quasi - bidirectional mode) i tl [3] - - - 660 ? a v dd = 5.5v, v in <2.0v internal pull - high resistor of /reset [1] r rst 15 - - k input low voltage (ttl input) v il - 0.3 - 0.2v dd - 0.1 v input low voltage (schmitt input) v il 1 - 0.3 0.3v dd v input low voltage ( /reset, xtal in) v il 2 - 0.3 0.15v dd v input high voltage (ttl input) v ih 0.2v dd +0.9 - v dd +0. 3 v input high voltage (schmitt input , /reset, xtal in ) v ih 1 0.7v dd - v dd +0. 3 v hysteresis voltage of (schmitt input) v hy - 0.2v dd - v source current (quasi - bidirectional mode) i oh - 360 - - ? a v dd = 4.5v, v s = 2.4v - 60 - - ? a v dd = 2.7v, v s = 2.2v - 50 - - ? a v dd = 2.5v, v s = 2.0v source current (push - pull mode) i oh1 - 25 - - ma v dd = 4.5v, v s = 2.4v - 4 - - ma v dd = 2.7v, v s = 2.2v - 3 - - ma v dd = 2.5v, v s = 2.0v sink current (quasi - bidirectional and push - pull mode) i ol 16 - - ma v dd = 4.5v, v s = 0.45v 10 - - ma v dd = 2.7v, v s = 0.45v 9 - - ma v dd = 2.5v, v s = 0.45v note: 1. /reset pin is a schmitt trigger input. 2. crystal input is a cmos input. 3. i/o pin can source a transition current when they are being externally driven from 1 to 0. in the condition of v dd =5.5v, 5he transition current reaches its maximum value when v in approximates to 2v .
m0519 nov. 02 , 201 6 page 58 of 69 rev 1 .0 2 m0519 datasheet ac electrical characteristics 7.3 note: duty cycle is 50%. symbol parameter condition min . typ . max . unit t chcx clock high time 1 0 - - ns t clcx clock low time 1 0 - - ns t clch clock rise time 2 - 1 5 ns t chcl clock fall time 2 - 1 5 ns 7.3.1 external 4~24mhz crystal parameter condition min . typ . . max . unit operation voltage v dd - 2. 5 - 5.5 v temperature - - 40 - 8 5 operating c urrent 12 mhz at v dd = 5v - 1 - ma c lock f requency external crystal 4 24 mhz typical crystal application circuits 7.3.1.1 crystal c1 c2 r 4 mhz ~ 24 mhz 10~20 pf 10~20 pf without figure 7 C 1 typical crystal application circuit t c h c x 9 0 % 1 0 % t c l c h t c h c l t c l c x t c l c l 0 . 3 v d d 0 . 7 v d d x t a l 2 x t a l 1 c 1 c 2 r
m0519 nov. 02 , 201 6 page 59 of 69 rev 1 .0 2 m0519 datasheet 7.3.2 internal 22.1184 mhz oscillator parameter condition min . typ . max . unit supply voltage - 2.5 - 5.5 v f requency (after calibration) - - 22.1184 - mhz +25 ? c ; v dd = 5v - 1 - +1 % - 40 to + 105 ? c ; v dd = 2.5v~5.5v - 2 - + 2 % operation current v dd =5v - 500 - ua 7.3.3 internal 10 khz oscillator parameter condition min . typ . max . unit supply voltage - 2.5 - 5.5 v center frequency - - 10 - khz calibrated internal oscillator frequency +25 ; v dd =5 v - 30 - +30 % - 40 ~+ 8 5 ; v dd =2.5 v~5.5 v - 50 - +50 %
m0519 nov. 02 , 201 6 page 60 of 69 rev 1 .0 2 m0519 datasheet analog characteristics 7.4 7.4.1 12 - bit saradc parameter symbol conditon min . typ . max . unit resolution - - - 12 bit differential nonlinearity error dnl - - 1~2 - 1~4 lsb integral nonlinearity error inl - 2 4 lsb offset error eo - 1 10 lsb full scale erro r eg - 1 1.005 lsb monotonic - guaranteed adc clock frequency f adc avdd = 5v - - 16 mhz avdd = 3v - - 8 sample rate f s avdd = 5v - - 8 00 ksps avdd = 3v - - 400 sample time t s - 8 - clock conversion time t adc - 1 2 - clock supply voltage av dd 2.5 - 5.5 v v re f voltage v ref 2.0 av dd supply current i dd a - 1.5 - ma reference curren t i re f - 1 - ma input voltage vin 0 - v ref v capacitance cin - 5 - pf 7.4.2 ldo parameter min . typ . max . unit note input voltage v dd 2. 5 5.5 v v dd input voltage output voltage 1.62 1.8 1.98 v v dd > 2.5 v operating temperature - 40 25 10 5 cbp - 1 - ? f r esr = 1 ? note: 1. it is recommended that a 10 uf or higher capacitor and a 100 nf bypass capacitor are connected between v dd and the closest v ss pin of the device. 2. to ensure power stability, a 1 ? f or higher capacitor must be connected between ldo_cap pin and the closest v ss pin of the device.
m0519 nov. 02 , 201 6 page 61 of 69 rev 1 .0 2 m0519 datasheet 7.4.3 low voltage reset parameter condition min . typ . max . unit operation v oltage - 0 - 5.5 v quiescent c urrent a v dd =5.5 v - 1 5 ? a operation t emperature - - 40 25 10 5 threshold v oltage - 1. 6 2.0 2. 4 v hysteresis - 0 0 0 v 7.4.4 brown - out detector parameter condition min . typ . max . unit operation v oltage - 0 - 5.5 v temperature - - 40 25 10 5 quiescent c urrent av dd =5.5 v - - 125 a brown - out v oltage bod_vl [1:0]=11 4. 2 4. 4 4.6 v bod_vl [1:0]=10 3. 5 3. 7 3.9 v bod_vl [1:0]=01 2.6 2.7 2.8 v bod_vl [1:0]=00 2. 1 2. 2 2. 3 v hysteresis - 30 - 150 mv 7.4.5 power - on reset (5v) parameter condition min . typ . max . unit operation temperature - - 40 25 10 5 reset v oltage v+ - 2 - v quiescent c urrent vin > reset voltage - 1 - na
m0519 nov. 02 , 201 6 page 62 of 69 rev 1 .0 2 m0519 datasheet 7.4.6 temperature sensor parameter conditions min . typ . max . unit operation v oltage [1] 2.5 - 5.5 v operation t emperature - 40 - 105 current c onsumption 6.4 - 10.5 a gain - 1.76 mv/ offset voltage temp=0 720 mv 7.4.7 comparator parameter condition min . typ . max . unit operation voltage a v dd - 2. 5 5.5 v operation temperature - - 40 25 8 5 operation c urrent v dd =3 .0 v - 20 40 a input o ffset v oltage - - 5 15 mv output s wing - 0.1 - v dd - 0.1 v input c ommon m ode r ange - 0.1 - v dd - 1.2 v dc g ain - - 70 - db propagation d elay vcm=1.2 v and vdiff=0.1 v - 200 - ns comparison v oltage 20 mv at vcm=1 v 50 mv at vcm=0.1 v 50 mv at vcm=v dd - 1.2 10 mv for non - hysteresis 10 20 - mv hysteresis vcm=0.4 v ~ v dd - 1.2 v - 10 - mv wake - up t ime cinp=1.3 v cinn=1.2 v - - 2 s
m0519 nov. 02 , 201 6 page 63 of 69 rev 1 .0 2 m0519 datasheet 7.4.8 op amplifier parameter condition min . typ . max . unit a vdd - 3.0 3 .3 5.5 v input offset voltage - - 2 5 mv input offset average drift - - 1 uv/ output swing - 0.1 - vdd - 0.1 v input common mode range - 0.1 - vdd - 1.2 v dc gain - - 8 0 - db unity gain freq. avdd=5v - - 5 mhz phase margin - 50 - psrr+ avdd=5v - 90 - db cmrr avdd=5v - 90 - db slew rate avdd=5v, rload=33k, cload=50p 6.0 - - v/us wake up time - - 1 us quiescent current - - 2 m a
m0519 nov. 02 , 201 6 page 64 of 69 rev 1 .0 2 m0519 datasheet flash dc electrical characteristics 7.5 symbol parameter conditions min . typ . max . unit v dd supply voltage 1.62 1.8 1.98 v [2] n endur endurance 10000 cycles [1] t ret data retention at 25 100 year t erase page erase time 20 ms t mer mass erase time 40 ms t prog program time 40 s i dd1 read current - 0.15 0.5 ma/mhz i dd2 program/erase current 7 ma note : this table is guaranteed by design, not test in production. [1] number of program/erase cycles. [2] v dd is source from chip ldo output voltage.
m0519 nov. 02 , 201 6 page 65 of 69 rev 1 .0 2 m0519 datasheet 8 package dimens i ons lqfp 100 v (14x14x1.4 mm footprint 2.0mm) 8.1 controlling dimension : millimeters 0.10 0 7 0 0.004 1.00 0.75 0.60 0.45 0.039 0.030 0.024 0.018 0.638 0.630 0.622 0.50 14.10 0.20 0.27 1.45 1.60 14.00 1.40 13.90 0.10 0.17 1.35 0.05 0.008 0.011 0.057 0.063 0.055 0.020 0.556 0.551 0.547 0.004 0.007 0.053 0.002 symbol min nom max max nom min dimension in inch dimension in mm a b c d e h d h e l y a1 a 2 l1 e 0.009 0.006 0.15 0.22 7 13.90 14.00 14.10 15.80 16.00 16.20 15.80 16.00 16.20 0.556 0.551 0.547 ? 0.638 0.630 0.622 d d e e b a2 a1 a l1 e c l y h h 1 100 ? 25 26 50 51 7 5 7 6
m0519 nov. 02 , 201 6 page 66 of 69 rev 1 .0 2 m0519 datasheet lqfp 64 s ( 7 x 7 x1.4 mm footprint 2.0 mm) 8.2
m0519 nov. 02 , 201 6 page 67 of 69 rev 1 .0 2 m0519 datasheet lqfp 48l (7x7x1.4mm footprint 2.0mm) 8.3 1 12 48 h h ? controlling dimension : millimeters 0.10 0 7 0 0.004 1.00 0.75 0.60 0.45 0.039 0.030 0.024 0.018 9.10 9.00 8.90 0.358 0.354 0.350 0.50 0.20 0.25 1.45 1.40 0.10 0.15 1.35 0.008 0.010 0.057 0.055 0.026 7.10 7.00 6.90 0.280 0.276 0.272 0.004 0.006 0.053 symbol min nom max max nom min dimension in inch dimension in mm a b c d e h d h e l y 0 a a l 1 1 2 e 0.008 0.006 0.15 0.20 7 0.020 0.35 0.65 0.10 0.05 0.002 0.004 0.006 0.15 9.10 9.00 8.90 0.358 0.354 0.350 7.10 7.00 6.90 0.280 0.276 0.272 0.014 37 36 25 24 13
m0519 nov. 02 , 201 6 page 68 of 69 rev 1 .0 2 m0519 datasheet 9 revision history date revision description 201 5 . 06 . 11 1.00 1. preliminary version. 201 6 . 0 7 . 3 1 1.01 1. added flash dc electrical characteristics in section 7.5 . 201 6 . 11 . 02 1.02 1. updated opa and adc item in 4.1.1 selection guide.
m0519 nov. 02 , 201 6 page 69 of 69 rev 1 .0 2 m0519 datasheet important notice nuvoton products are neither intended nor warranted for usage in systems or equipment, any malfunction or failure of which may cause loss of human life, bodily injury or severe property damage. such applications are deemed, insecure usage. insecure usag e includes, but is not limited to: equipment for surgical implementation, atomic energy control instruments, airplane or spaceship instruments, the control or operation of dynamic, brake or safety systems designed for vehicular use, traffic signal instrume nts, all types of safety devices, and other applications intended to support or sustain life. all insecure usage shall be made at customers risk, and in the event that third parties lay claims to nuvoton as a result of customers insecure usage, custome r shall indemnify the damages and liabilities thus incurred by nuvoton.

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